dcd Project Status (10/11/2009 - 23:53:30)
Project File: dcd.ise Current State: Programming File Generated
Module Name: dcd2test
  • Errors:
No Errors
Target Device: xc3s500e-4fg320
  • Warnings:
1 Warning
Product Version: ISE 10.1.03 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
dcd Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 24 9,312 1%  
Number of 4 input LUTs 11 9,312 1%  
Logic Distribution     
Number of occupied Slices 18 4,656 1%  
    Number of Slices containing only related logic 18 18 100%  
    Number of Slices containing unrelated logic 0 18 0%  
Total Number of 4 input LUTs 33 9,312 1%  
    Number used as logic 11      
    Number used as a route-thru 22      
Number of bonded IOBs
Number of bonded 14 232 6%  
Number of BUFGMUXs 1 24 4%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSun Oct 11 23:52:57 2009000
Translation ReportCurrentSun Oct 11 23:53:02 2009000
Map ReportCurrentSun Oct 11 23:53:07 2009002 Infos
Place and Route ReportCurrentSun Oct 11 23:53:18 200901 Warning3 Infos
Static Timing ReportCurrentSun Oct 11 23:53:22 2009003 Infos
Bitgen ReportCurrentSun Oct 11 23:53:28 2009000

Date Generated: 10/11/2009 - 23:53:30