dcd Project Status (10/11/2009 - 23:53:30) | |||
Project File: | dcd.ise | Current State: | Programming File Generated |
Module Name: | dcd2test |
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No Errors |
Target Device: | xc3s500e-4fg320 |
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1 Warning |
Product Version: | ISE 10.1.03 - WebPACK |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Timing Report) |
dcd Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 24 | 9,312 | 1% | ||
Number of 4 input LUTs | 11 | 9,312 | 1% | ||
Logic Distribution | |||||
Number of occupied Slices | 18 | 4,656 | 1% | ||
Number of Slices containing only related logic | 18 | 18 | 100% | ||
Number of Slices containing unrelated logic | 0 | 18 | 0% | ||
Total Number of 4 input LUTs | 33 | 9,312 | 1% | ||
Number used as logic | 11 | ||||
Number used as a route-thru | 22 | ||||
Number of bonded IOBs | |||||
Number of bonded | 14 | 232 | 6% | ||
Number of BUFGMUXs | 1 | 24 | 4% |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sun Oct 11 23:52:57 2009 | 0 | 0 | 0 | |
Translation Report | Current | Sun Oct 11 23:53:02 2009 | 0 | 0 | 0 | |
Map Report | Current | Sun Oct 11 23:53:07 2009 | 0 | 0 | 2 Infos | |
Place and Route Report | Current | Sun Oct 11 23:53:18 2009 | 0 | 1 Warning | 3 Infos | |
Static Timing Report | Current | Sun Oct 11 23:53:22 2009 | 0 | 0 | 3 Infos | |
Bitgen Report | Current | Sun Oct 11 23:53:28 2009 | 0 | 0 | 0 |