Device Usage Page (device_usage_statistics.html)

This HTML page displays the device usage statistics that will be sent to Xilinx. The file also contains predefined XML tags used to simplify processing.
 
Please verify the contents are okay to send to Xilinx!
 

 
Software Version and Target Device
Product Version: ISE:10.1.03 (WebPACK) Target Family: spartan3e
OS Platform: NT Target Device: xc3s500e
Project ID (random number) 25095.15439.1 Target Package: fg320
Registration ID 1A1NAG3LAMJXSWSEX1KEG24DN Target Speed: -4
Date Generated Sun Oct 11 23:53:29 2009
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Counters=2
  • 16-bit up counter=1
  • 8-bit up counter=1
MiscellaneousStatistics
  • AGG_BONDED_IO=14
  • AGG_IO=14
  • AGG_SLICE=18
  • NUM_4_INPUT_LUT=33
  • NUM_BONDED_IBUF=2
  • NUM_BONDED_IOB=12
  • NUM_BUFGMUX=1
  • NUM_CYMUX=22
  • NUM_LUT_RT=22
  • NUM_SLICEL=18
  • NUM_SLICE_FF=24
  • NUM_XOR=24
NetStatistics
  • NumNets_Active=60
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=12
  • NumNodesOfType_Active_CNTRLPIN=16
  • NumNodesOfType_Active_DOUBLE=56
  • NumNodesOfType_Active_DUMMY=57
  • NumNodesOfType_Active_DUMMYESC=2
  • NumNodesOfType_Active_GLOBAL=6
  • NumNodesOfType_Active_HUNIHEX=7
  • NumNodesOfType_Active_INPUT=79
  • NumNodesOfType_Active_IOBOUTPUT=2
  • NumNodesOfType_Active_OMUX=40
  • NumNodesOfType_Active_OUTPUT=44
  • NumNodesOfType_Active_PREBXBY=1
  • NumNodesOfType_Active_VFULLHEX=2
  • NumNodesOfType_Active_VUNIHEX=4
  • NumNodesOfType_Gnd_DOUBLE=1
  • NumNodesOfType_Gnd_INPUT=2
  • NumNodesOfType_Gnd_OMUX=1
  • NumNodesOfType_Gnd_OUTPUT=2
  • NumNodesOfType_Gnd_PREBXBY=3
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=2
  • IBUF_INBUF=2
  • IBUF_PAD=2
  • IOB=12
  • IOB_OUTBUF=12
  • IOB_PAD=12
  • SLICEL=18
  • SLICEL_C1VDD=2
  • SLICEL_CYMUXF=12
  • SLICEL_CYMUXG=10
  • SLICEL_F=18
  • SLICEL_FFX=12
  • SLICEL_FFY=12
  • SLICEL_G=15
  • SLICEL_GNDF=10
  • SLICEL_GNDG=10
  • SLICEL_XORF=12
  • SLICEL_XORG=12
 
Configuration Data
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:2]
  • PULL=[PULLDOWN:1]
IOB_PAD
  • DRIVEATTRBOX=[12:12]
  • IOATTRBOX=[LVCMOS25:12]
  • SLEW=[SLOW:12]
SLICEL_FFX
  • FFX_INIT_ATTR=[INIT0:12]
  • FFX_SR_ATTR=[SRLOW:12]
  • LATCH_OR_FF=[FF:12]
  • SYNC_ATTR=[ASYNC:12]
SLICEL_FFY
  • FFY_INIT_ATTR=[INIT0:12]
  • FFY_SR_ATTR=[SRLOW:12]
  • LATCH_OR_FF=[FF:12]
  • SYNC_ATTR=[ASYNC:12]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IBUF
  • I=2
  • PAD=2
IBUF_INBUF
  • IN=2
  • OUT=2
IBUF_PAD
  • PAD=2
IOB
  • O1=12
  • PAD=12
IOB_OUTBUF
  • IN=12
  • OUT=12
IOB_PAD
  • PAD=12
SLICEL
  • BX=2
  • CE=4
  • CIN=10
  • CLK=12
  • COUT=10
  • F1=18
  • F2=6
  • F3=6
  • F4=4
  • G1=15
  • G2=3
  • G3=3
  • G4=1
  • SR=12
  • X=6
  • XQ=12
  • Y=3
  • YQ=12
SLICEL_C1VDD
  • 1=2
SLICEL_CYMUXF
  • 0=12
  • 1=12
  • OUT=12
  • S0=12
SLICEL_CYMUXG
  • 0=10
  • 1=10
  • OUT=10
  • S0=10
SLICEL_F
  • A1=18
  • A2=6
  • A3=6
  • A4=4
  • D=18
SLICEL_FFX
  • CE=4
  • CK=12
  • D=12
  • Q=12
  • SR=12
SLICEL_FFY
  • CE=4
  • CK=12
  • D=12
  • Q=12
  • SR=12
SLICEL_G
  • A1=15
  • A2=3
  • A3=3
  • A4=1
  • D=15
SLICEL_GNDF
  • 0=10
SLICEL_GNDG
  • 0=10
SLICEL_XORF
  • 0=12
  • 1=12
  • O=12
SLICEL_XORG
  • 0=12
  • 1=12
  • O=12
 
Tool Usage
Command Line History
  • xst -ise <ise_file>
  • xst -ise <ise_file>
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s500e-fg320-4 -cm area -pr off -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
 
>
Software Quality
Run Statistics
ProgramRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 7 7 0 0 0 0 0
bitgen 48 48 0 0 0 0 0
map 51 50 0 0 0 0 0
ngdbuild 61 61 0 0 0 0 0
par 50 50 0 0 0 0 0
trce 50 50 0 0 0 0 0
xst 60 60 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/pce_c_constraining_a_design.htm ( 1 ) /doc/usenglish/isehelp/spartan3e/libs_le_m2_1.htm ( 2 )
/doc/usenglish/isehelp/sse_c_bus_names.htm ( 1 ) /doc/usenglish/isehelp/sse_c_name_nets_to_bus.htm ( 1 )
/doc/usenglish/isehelp/sse_c_nets.htm ( 1 ) /doc/usenglish/isehelp/sse_c_overview.htm ( 1 )
/doc/usenglish/isehelp/sse_c_schematics.htm ( 1 ) /doc/usenglish/isehelp/sse_db_rename_net.htm ( 1 )
/doc/usenglish/isehelp/sse_n_adding_bus_tap.htm ( 1 ) /doc/usenglish/isehelp/sse_p_adding_bus_tap_autonaming.htm ( 1 )
/doc/usenglish/isehelp/sse_p_adding_bus_tap_during_wiring.htm ( 1 ) /doc/usenglish/isehelp/sse_p_adding_bus_tap_manually.htm ( 1 )
/doc/usenglish/isehelp/sse_p_connecting_bus_io.htm ( 1 ) /doc/usenglish/isehelp/sse_p_connecting_net_bus.htm ( 1 )
/doc/usenglish/isehelp/sse_p_creating_bus.htm ( 1 ) /doc/usenglish/isehelp/sse_p_naming_bus.htm ( 1 )
/doc/usenglish/isehelp/sse_p_naming_net.htm ( 1 ) /doc/usenglish/isehelp/sse_p_routing_wire_auto.htm ( 1 )
 
Project Statistics
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_Simulator=ISE Simulator (VHDL/Verilog)
PROP_Top_Level_Module_Type=HDL PROP_PreferredLanguage=Verilog
PROP_Enable_Message_Filtering=false PROP_Enable_Incremental_Messaging=false
PROP_UseSmartGuide=false Partitions count=1
FILE_UCF=1 FILE_VERILOG=3
PROP_DevDevice=xc3s500e PROP_DevFamily=Spartan3E
PROP_DevPackage=fg320 PROP_DevSpeed=-4
PROP_FitterReportFormat=HTML PROP_Simulator=ISE Simulator (VHDL/Verilog)
PROP_UserConstraintEditorPreference=Constraints Editor Project duration(days)=0