sum Project Status (10/12/2009 - 00:02:11)
Project File: sum.ise Current State: Programming File Generated
Module Name: addSub
  • Errors:
No Errors
Target Device: xc3s500e-4fg320
  • Warnings:
No Warnings
Product Version: ISE 10.1.03 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
 
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
sum Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 7 9,312 1%  
Logic Distribution     
Number of occupied Slices 4 4,656 1%  
    Number of Slices containing only related logic 4 4 100%  
    Number of Slices containing unrelated logic 0 4 0%  
Total Number of 4 input LUTs 7 9,312 1%  
Number of bonded IOBs
Number of bonded 9 232 3%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Oct 12 00:01:41 2009000
Translation ReportCurrentMon Oct 12 00:01:47 2009000
Map ReportCurrentMon Oct 12 00:01:51 2009002 Infos
Place and Route ReportCurrentMon Oct 12 00:02:00 2009001 Info
Static Timing ReportCurrentMon Oct 12 00:02:04 2009003 Infos
Bitgen ReportCurrentMon Oct 12 00:02:10 2009000

Date Generated: 10/12/2009 - 00:02:11