sum Project Status (10/12/2009 - 00:02:11) | |||
Project File: | sum.ise | Current State: | Programming File Generated |
Module Name: | addSub |
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No Errors |
Target Device: | xc3s500e-4fg320 |
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No Warnings |
Product Version: | ISE 10.1.03 - WebPACK |
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All Signals Completely Routed |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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0 (Timing Report) |
sum Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of 4 input LUTs | 7 | 9,312 | 1% | ||
Logic Distribution | |||||
Number of occupied Slices | 4 | 4,656 | 1% | ||
Number of Slices containing only related logic | 4 | 4 | 100% | ||
Number of Slices containing unrelated logic | 0 | 4 | 0% | ||
Total Number of 4 input LUTs | 7 | 9,312 | 1% | ||
Number of bonded IOBs | |||||
Number of bonded | 9 | 232 | 3% |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Mon Oct 12 00:01:41 2009 | 0 | 0 | 0 | |
Translation Report | Current | Mon Oct 12 00:01:47 2009 | 0 | 0 | 0 | |
Map Report | Current | Mon Oct 12 00:01:51 2009 | 0 | 0 | 2 Infos | |
Place and Route Report | Current | Mon Oct 12 00:02:00 2009 | 0 | 0 | 1 Info | |
Static Timing Report | Current | Mon Oct 12 00:02:04 2009 | 0 | 0 | 3 Infos | |
Bitgen Report | Current | Mon Oct 12 00:02:10 2009 | 0 | 0 | 0 |